Towards High-Performance and Energy-Efficient Memory Hierarchy

Chip MultiProcessors (CMPs) are becoming the de facto hardware architecture over a range of computing platforms. According to Moore's law, the number of cores in CMPs is expected to keep growing as transistor density continues to shrink. As the number of cores increases, the complexity and trade-offs of current CMP design shift towards the uncore part of the chip. In this book, we discuss several approaches to improve the performance and energy efficiency of uncore components at major levels of the uncore subsytem such as the Last Level Cache (LLC) and the interconnect.