Multithreaded Programming and Execution Models for Reconfigurable Hardware

Modern platform FPGAs integrate programmable logic with dedicated microprocessors and present powerful implementation platforms for complete reconfigurable systems-on-chip. However, traditional design techniques that view specialized hardware circuits as passive coprocessors are ill-suited for programming these reconfigurable computers. Moreover, the promising feature of partial reconfiguration has yet to be embraced by a pervasive programming paradigm. In this thesis, we present fundamental work in the new area of multithreaded programming of reconfigurable logic devices. We propose an execution environment called ReconOS that is based on existing embedded operating systems and extends the multithreaded programming model--already establishedand highly successful in the software domain--to reconfigurable hardware. Using threads and common synchronization and communication services as an abstraction layer, our design and execution platforms allow for the creation of portable and flexible multithreaded HW/SW applications for CPU/FPGA systems.