Investigation on Routing Methods in Low power VLSI Scenario

The ever-increasing demand in new applications and compact devices resulted in developing new technologies in the integration level. Very large scale integration (VLSI) has given the advantage of integrating large density applications into a compact platform achieving the objective of obtaining high-end applications onto a single platform.With the increase in developing the integration density, this technology has evolved to Nanoscale designing, which gives a significant leap into the VLSI domain. With the achievement of large integration density, the constraints of power, speed and throughput are also increasing. As the transistor density increase, the power consumption too increases. This is a bottleneck for VLSI design for critical applications. Hence the need for lower power consumption is a major objective in the VLSI design environment. Power optimization is developed via multiple means, where researchers have an outcome with various approaches in composition level or integration level to reduce power dissipation. The processing power utilization is considered a useful consumption, however, power losses due to IR losses and electromagnetic interference (EMI) are investigated.