High-Performance Embedded Computing

Performance Microprocessors Reliability Smart cards Cost Turing machines Verification Software radio Avionics Modeling Quality Petri nets Software architecture Arm Validation Countermeasures CMOS Digital rights management configuration networking Metrics Threads SRAM Methodologies Multithreading Video compression standards Task parallelism Audio compression Finite State Machine Safety-critical Systems Physical Security Vectors Error-Correction Markov-Models Applications Atom Error detection Engine control Testing Techniques Streams Service Discovery Vectorization Architectures Wireless VLIW Expressiveness Power Attack Physical layer RISC Network organization Voting Systems Data parallelism MIPs Motion estimation Reliability Methods Embedded Multiple streams Instruction-level parallelism Dynamic Scheduling DVFS Communication styles Design tasks Scratch pads Personal Area Networks CISC Huffman coding actions after faults address bus encoding attacks on automobiles attacks on sensor networks applications demand reliability baseband layer basic data flow graphs area model Arithmetic Coding block size versus compression ratio branches in compressed code branch patching cache models cache parameters and behavior battery attack audio encoder branch tables characterizing faults blocking vs. unblocking combined wireless/network communications configurable caches bus encoding cache design code compression metrics design repeatability busses cache parameter selection data operand sizes buffering and communication bus-invert coding design diversity Energy Model data compression algorithms delay model finite vs. infinite state fixed-point method for arithmetic coding Digital Demodulation error-aware computing communication in FSMs code compression co-design flows compressed code blocks compression for energy savings compression and encryption Control Flow Graph control-oriented languages control flow models cryptography and CPUs design time dictionary-based bus encoding harnesses vs. networks heterogeneity and interoperability JPEG 2000 Kahn process networks energy/power error correction codes error signal link manager memory controllers lossy compression and perceptual coding middleware group protocols joint algorithm and architecture development language styles Lempel-Ziv coding new problems logic-level reliability memory arrays memory block structure multiple issue hardware design methodologies MXT memory system physical access platform-based design non-control uses pre-cache decompression QoS attacks reference implementations power attacks platform design phases pros and cons of standards single issue service discovery protocol Signal Flow Graphs register file design Lempel-Ziv-Welch coding sources of faults synthesized compressed code specialized automotive networks synthesis and simulation simulator-in-the-loop system reliability metrics split register files transition-based error analysis subword parallelism Intel Atom task graphs internet attacks watchdog timers waterfall and spiral the design productivity gap Wolfe and Chanin evaluation software-based decompression working-zone encoding static scheduling variable-length codewords varieties of parallelism multi-ported memories verification and finite state non-metric characteristics L2CAP layer multimedia algorithms programming platforms Razor microarchitecture microarchitecture with code decompression parallelism and architecture multimedia benchmarks self-reprogramming architecture static vs. dynamic RFCOMM variable-to-fixed encoding post-cache decompression Power Architecture transport group protocols varieties of performance software radio tiers register file parameters synchronous data flow synchronous languages two-stage process varieties of attacks verification and design