Architectural exploration in Network on Chip (NoC)

Today's users demand high-performance embedded systems capable of delivering high computing power. The evolution of embedded systems poses a design challenge, as these systems have to find a compromise between their capabilities (computing power, dynamism) and the constraints of embedded systems (silicon area, power consumption). The solution to the computing power problem is to switch to multiprocessor systems (MPSoCs). In addition, networks-on-a-chip (NOCs) have emerged to cope with inter-communication limitations such as bus, hierarchical bus and point-to-point. Network-on-Chip (NoC)-based interconnection infrastructure is becoming the preferred approach for facilitating communication between processing elements (PEs) in MPSoCs. It is more efficient to integrate several small specialized or non-specialized processors interconnected by a network-on-chip (NoC) whose energy and silicon efficiency are better than increasing the performance of a single processor. The aim of this work is to provide an overview of architectural exploration on NoCs.